Dr. Aakash Kumar Jain

Assistant Professor

E-mail: akjain@iiitdm.ac.in | Ph: 04427476111 | Room No: 310-M



New Delhi



IIT Bombay


M. Tech



  1. Nanoscale Low Power Semiconductor Devices for IoT applications

  2. Wide-Bandgap semiconductor Power Devices

  3. Emerging memory and advanced logic Devices for Neuromorphic computing

Research Interests

  1. Motivated candidates interested in doing Ph.D. Thesis in the following research areas can reach out to me on Email-

  2. Silicon and Silicon Carbide based Emerging MOSFET device Modelling,

  3. Emerging Non Volatile Memory Device Modeling for Reconfigurable computing and Emerging Applications

  4. Device-Circuit Co-design for In-memory Computation

  5. DTCO

  6. Spintronics and 2-D materials based devices for logic and Memory

  7. Quantum Computing

  8. Neuromorphic computing using FPGA

  9. Machine learning -TCAD Interface

  10. Physics based analysis of Semiconductor process technologies

Honours + Awards + Recognitions

  1. Received the prestigious DST India's SERB-ITS travel grant in July 2022 for attending 12th SiNano Modeling and Simulation Summer School held at University of Glasgow, Scotland from 12th- 14th July 2022.

Work Experience


  1. Assistant Professor-March 2021 onwards


  1. Postdoctoral Research Fellow at NUS Singapore for 1.5 years

Professional Membership

  1. IEEE Member

Professional Service

  1. Reviewer of IEEE J-EDS, IEEE Access and IEEE TCAS-1


  1. Spring 2023: Digital IC Design

  2. Spring 2023: IC Design Laboratory

  3. Autumn 2022: Network theory

  4. Autumn 2022: Analog Circuits Practice Laboratory

  5. Autumn 2022: Digital Circuits Practice Laboratory

  6. Spring 2022: Digital IC Design

  7. Spring 2022: Embedded Systems Laboratory

  8. Autumn 2021: Electronic Manufacturing and Prototyping

  9. Autumn 2021: VLSI System Design

  10. Autumn 2021: VLSI System Design Laboratory

Journal Publications

  1. A. K. Jain and A. Singha, "Sub-10 nm scalability of emerging Nanowire Junctionless FETs using a Schottky metallic Core," Journal of Electronic Materials, January 2021.

  2. A. K. Jain, and M. Jagadesh Kumar, “Sub-10 nm scalability of SOI-JLFETs using a ground plane in a high-K BOX: A Simulation Study,” IEEE Access, Vol. 8, pp. 137540-137548, July 2020.

  3. A. K. Jain, Jaspreet Singh, and M. Jagadesh Kumar, “Investigation of the scalability of the emerging Nanotube Junctionless FETs using an intrinsic pocket,” IEEE Journal of the Electron Devices Soc., Vol. 7, pp 888-896, Aug. 2019.

  4. J. Singh, A.K. Jain, and M. Jagadesh Kumar, “Realizing a Planar 4H-SiC Junctionless FET for Sub-10-nm Regime Using P+ Pocket,” IEEE Transactions on Electron Devices, vol. 66, no. 7. pp. 3209- 3204, July 2019.

  5. A. K. Jain, S. Sahay, and Mamidala Jagadesh Kumar, “Controlling L-BTBT in Emerging Nanotube FETs using Dual-material gate,” IEEE Journal of the Electron Devices Soc., vol. 6, pp. 611- 621, Apr. 2018.

  6. A.K. Jain, S. Yadav, M. Mehra, S. Sapra, & M. Singh, “Solution-Processed Cubic GaN for Potential Lighting Applications,” MRS Advances, Vol. 4, Issue 9, pp. 1-8, Feb. 2019.

Conference Publications

  1. Sudhanshu Shekhar, Bhupendra Reniwal, and A.K. Jain, "Mitigating L-BTBT induced Leakage current in Emerging Nanosheet Junctionless Accumulation Mode FETs", 11th International CCSN Conference, September 2022.

  2. A. K. Jain, J. Singh, and M. Jagadesh Kumar, “Investigating the scalability of Nanowire Junctionless Accumulation mode FETs, using an Intrinsic Pocket,” in 45th IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), San Jose, California, USA, Oct. 2019.

  3. A. K. Jain, G. Musalgaonkar, and M. Jagadesh Kumar, “Controlling L-BTBT in ultra-short channel nanowire accumulation mode FETs using gate-on-drain overlap,” in 5th Joint EUROSOI-ULIS, Grenoble, April 2019.

  4. A. K. Jain, and M. Jagadesh Kumar, “Investigating the doping profiles in emerging nanowire Junctionless Accumulation mode FETs from the L-BTBT perspective,” 3rd IEEE EDTM Conference, Singapore, March 2019.

  5. A. K. Jain, S. Yadav, M. Mehra, S. Sapra, and M. Singh, “Solution-Processed Cubic GaN for Potential Lighting Applications”, MRS Fall 2018, Boston, Massachusetts, USA, Nov. 2018.

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