Dr. Aakash Kumar Jain

Assistant Professor

E-mail: akjain@iiitdm.ac.in | Room No: 310-M



New Delhi



IIT Bombay


M. Tech



  1. Nanoscale Low Power Semiconductor Devices for IoT applications

  2. Wide-Bandgap semiconductor Devices

  3. Emerging memory Devices

  4. In-memory Computation for Neuromorphic computing

Research Interests

  1. Silicon and Silicon Carbide based Emerging MOSFET device Modelling,

  2. Emerging Non Volatile Memory Device Modeling for Reconfigurable computing and Emerging Applications

  3. Device-Circuit Co-design for In-memory Computation

  4. Solution Processed Semiconductor devices for Next generation electronics

  5. Spintronics and 2-D materials based devices for logic and Memory

  6. Brain-Machine interfacing

Work Experience


  1. Postdoctoral Research Fellow at NUS Singapore

Professional Membership

  1. IEEE Member

Professional Service

  1. Reviewer of IEEE J-EDS, IEEE Access and IEEE TCAS-1


  1. Electronic Manufacturing and Prototyping- Autumn semester 2021

  2. VLSI System Design- Autumn semester 2021

  3. VLSI System Design Laboratory- Autumn semester 2021

Journal Publications

  1. A. K. Jain and A. Singha, "Sub-10 nm scalability of emerging nanowire junctionless FETs using a Schottky metallic Core," Springer Journal of Electronic Materials, January 2021.

  2. A. K. Jain, and M. Jagadesh Kumar, “Sub-10 nm scalability of SOI-JLFETs using a ground plane in a high-K BOX: A Simulation Study,” IEEE Access, Vol. 8, pp. 137540-137548, July 2020.

  3. A. K. Jain, Jaspreet Singh, and M. Jagadesh Kumar, “Investigation of the scalability of the emerging Nanotube Junctionless FETs using an intrinsic pocket,” IEEE Journal of the Electron Devices Soc., Vol. 7, pp 888-896, Aug. 2019.

  4. J. Singh, A.K. Jain, and M. Jagadesh Kumar, “Realizing a Planar 4H-SiC Junctionless FET for Sub-10-nm Regime Using P+ Pocket,” IEEE Transactions on Electron Devices, vol. 66, no. 7. pp. 3209- 3204, July 2019.

  5. A. K. Jain, S. Sahay, and Mamidala Jagadesh Kumar, “Controlling L-BTBT in Emerging Nanotube FETs using Dual-material gate,” IEEE Journal of the Electron Devices Soc., vol. 6, pp. 611- 621, Apr. 2018.

  6. A.K. Jain, S. Yadav, M. Mehra, S. Sapra, & M. Singh, “Solution-Processed Cubic GaN for Potential Lighting Applications,” MRS Advances, Vol. 4, Issue 9, pp. 1-8, Feb. 2019.

Conference Publications

  1. A. K. Jain, J. Singh, and M. Jagadesh Kumar, “Investigating the scalability of Nanowire Junctionless Accumulation mode FETs, using an Intrinsic Pocket,” in 45th IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), San Jose, California, USA, Oct. 2019.

  2. A. K. Jain, G. Musalgaonkar, and M. Jagadesh Kumar, “Controlling L-BTBT in ultra-short channel nanowire accumulation mode FETs using gate-on-drain overlap,” in 5th Joint EUROSOI-ULIS, Grenoble, April 2019.

  3. A. K. Jain, and M. Jagadesh Kumar, “Investigating the doping profiles in emerging nanowire Junctionless Accumulation mode FETs from the L-BTBT perspective,” 3rd IEEE EDTM Conference, Singapore, March 2019.

  4. A. K. Jain, S. Yadav, M. Mehra, S. Sapra, and M. Singh, “Solution-Processed Cubic GaN for Potential Lighting Applications”, MRS Fall 2018, Boston, Massachusetts, USA, Nov. 2018.

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