1. Nanoelectronics

2. Device Modeling and Simulation

3. Semiconductor Devices

4. Neuromorphic Computing

1. Compact Model, TCAD Simulations, SOI MOSFETs, FinFETs, Negative Capacitance FETs, Radiation Hardened Devices, Ferroelectric FETs, Solar Cells, Graphene FET, Neuromorphic Computing, FET based Biosensors, Machine Learning in TCAD

1. Selected as one of the recipients for the IEEE Madras Section Publication Award 2022.

2. Received grant from IEEE Electron Devices Society (EDS) of $10000 to organize the Summer School on "Neuromorphic Computing Devices and Circuits".

3. Received grant from Accelerate Vigyan Vritika Scheme to take internship students and train them in "Neuromorphic Device Implementation"

4. Selected for IEEE MAS BEST RESEARCHER AWARD -2021 (Age 40 and Below) from IEEE Madras Section.

5. Selected as one of the recipients for the IEEE Madras Section Publication Award 2021.

6. Elevated to IEEE Senior Member.

7. Received Startup Research Grant (SRG) from Science Engineering Research Board (SERB), DST, GoI, 2020.

8. TPC member of 8th International Conference on Signal Processing and Integrated Networks (SPIN 2021).

9. Co-Chaired a session in 2021 Springer International Conference on Micro/Nanoelectronics Devices, Circuits, and Systems (MNDCS-2021) in Track 6 on 30/01/2021.

10. Chaired a Session in 4th International Conference on Information and Communication Technology (CICT), 2020.

11. Chaired a Session in 1st IEEE International Conference on Energy, Systems and Information Processing (IEEE ICESIP) 2019.

12. Organizing Committee Member of 4th International Conference on Information and Communication Technology (CICT), 2020.

13. Received Recognition and Medal from IEEE Madras Section, 2020

14. Listed in the Golden Reviewers List of 2020 by IEEE Transactions on Electron Devices

15. Received Recognition and Medal from IEEE Madras Section, 2019

16. Snigdhashri Patra Memorial Gold Medal for Best Ph.D. Thesis of 2016-17 by National Institute of Technology Rourkela

17. TPC of Modeling and Simulation Group in IEEE Electron Devices Technology and Manufacturing (EDTM) Conference 2020.

18. Availed International Travel Grant from SERB, DST under Young Scientist Award, 2016

19. Best paper award in the virtual presentation in ICMCC, San Diego, 2015

20. Reviewer of IEEE Transactions on Electron Devices

21. Reviewer of IEEE Electron Device Letters

22. Reviewer of 2D Materials, IOP Science

23. Reviewer of IET Circuits, Devices & Systems

24. Member of Editorial Board of Frontiers of Mechatronics

25. Member of TPC in International Conference on Signal Processing and Communication (ICSC-2018)

26. Reviewer of Microelectronics Journal, Superlattices & Microstructures, Material Science in Semiconductor Processing, Physica-E: Low Dimensional Systems & Nanostructures, Elsevier

27. Reviewer of Nanotechnology, IOP Science

28. Reviewer of International Journal of Electronics, Taylor & Francis

29. Reviewer of Analog Integrated Circuit & Signal Processing, Pramana Journal of Physics, Springer

Teaching

1. Assistant Professor in Electronics & Communication Engineering in Jaypee Institute of Information Technology Noida from July 2017 to March 2018

Research

1. Senior Project Engineer at Nanolab, Indian Institute of Technology Kanpur from March-July, 2017

1. Senior Member, Institute of Electrical and Electronics Engineers (IEEE)

2. Senior Member, Electron Devices Society (EDS), IEEE

3. Life Member of Institute of Engineers (IE), India

4. Life Member of Solar Energy Society of India (SESI)

1. The details of the events (Distinguished Lectures, Technical Talks, etc.) organized by IIITDM EDS SBC can be found from the corresponding website.

2. Organized five-days in-person IEEE EDS sponsored summer school on "Neuromorphic Computing"

3. Organized six-days virtual international workshop virtual short term course on "Research Opportunities in "Semiconductor Materials and Devices" ROSMD-2022" during Oct 19-24, 2022.

4. Organized five-days virtual short term Training Program on "Technical Writing, Presentation and Scientific Research with Advanced Computing Tools: Hands-On Training" during Dec 06-10, 2021.

5. Organized five-days virtual short term course on "Research Opportunities in "Semiconductor Materials and Devices" ROSMD-2021" during Oct 22-26, 2021.

6. Organized five-days virtual short term course on "Research Opportunities in "Semiconductor Materials and Devices" ROSMD-2020" during Oct 22-26, 2020.

7. Delivered an in-person talk on "Mimicking of Biological Behavior Through CMOS and Beyond CMOS Based Devices" in in the 7-days High-end workshop on "Brain-inspired/Neuromorphic Computing for Responsible AI" funded by SERB and organized by IIT Patna on 23/03/2023.

8. Delivered Talk on "Mimicking of Biological Behavior Through Emerging Nanoelectronic Devices" in IEEE EDS sponsored summer school on Neuromorphic Computing organized by IIITDM Kancheepuram during 19-23 Dec 2022.

9. Invited talk on in IEEE International Conference on Emerging Electronics (ICEE) during 12-14 Dec 2022.

10. Invited talk on "Single Layer Substitution Doped Graphene FET: From Numerical Model to Extremely Closed-Form Region-wise Model and Application to Synaptic Plasticity" in the 6-days International workshop Research Opportunities in Semiconductor Materials and Devices (ROSMD) jointly organized by SRM Institute of Science and Technology and IIITDM Kancheepuram on 20/10/2022.

11. Invited talk on "Emerging Semiconductor Devices in the World of Nanoelectronics" in the 5-days IEEE EDS Sponsored Summer School on celebration of 75th years of transistor invention organized by NIT Silchar on 24/08/2022.

12. Invited Talk on "Emerging Semiconductor Devices in the World of Nanoelectronics" in the 5-days FDP on Emerging Trends & Practical Applications on VLSI Design" organized by Aditya College of Engineering on 04/08/2022.

13. Invited talk on "Emerging Semiconductor Devices in the World of Nanoelectronics" in the 7-days FDP "Outcome based research: VLSI devices, circuit analysis, latest design tools and applications" organized by JIIT Noida on 21/07/2022.

14. Invited Talk on "Electronic Transport Properties and Modeling of B/N Substitution Doped Graphene FET" in the 3-days IEEE EDS Workshop on Devices and Circuits (WDC), Goa organized by IIT Kanpur and IEEE ED UP Section on 26/03/2022.

15. Invited Talk on "Futuristic Nanoelectronic Materials and Devices: Opportunities and Challenges" in the 6-days AICTE sponsored QIP STC on "Frontiers in materials research: from materials simulation to emerging applications" organized by IIITDM Kancheepuram on 25/03/2022.

16. Invited Talk on "Futuristic Nanoelectronic Materials and Devices: Opportunities and Challenges" in the 10-days FDP on "Nanoscaled Devices and Internet of Things for Engineering Applications" organized by E & ICT Academy, NIT Warangal on 24/02/2022.

17. Invited talk on "Next Generation Solar Cells for terrestrial and Space Applications" in the 6-days AICTE sponsored QIP STC on "Emerging Applications of Engineering Electromagnetics" organized by IIITDM Kancheepuram on 21/02/2022.

18. Invited talk on "Futuristic Nanoelectronic Materials and Devices: Opportunities and Challenges" in the 5-days FDP on "Advanced Semiconductor Material and Devices (ASMD 2022)" organized by Vellore Institute of Technology, Chennai on 10/01/2022.

19. Invited talk on "Futuristic Nanoelectronic Materials and Devices: Opportunities and Challenges" in the 5-days FDP on "Next Generation Materials and Devices" organized by SR University, Warangal on 07/01/2022.

20. Invited Talk on "Nanoscale Transistors for Integrated Circuits" in the 6-days FDP on "Recent Advancements in Organic and Nano Electronics" organized by SRM Institute of Science and Technology on 10/10/2021.

21. Invited Talk on "Practicing hands-on exercises and examples (LaTeX)" in the 5-days IEEE Online National Workshop on Research Methodology organized by IEEE Student Branch, IIITDM Kancheepuram.

22. Invited Talk on "Nanoscale Devices: Challenges and Opportunities" in the 5-days AICTE sponsored FDP on "Future Perspective of Semiconductor Devices" organized by Kalasalingam Academy of Research and Education on 22/06/2021.

23. Invited Talk on "Nanoscale Devices: Challenges and Opportunities" in the 5-days AICTE sponsored FDP on "Recent Advances and Challenges in Nanoscale Devices: Design, Materials, and Applications Perspective" organized by National Institute of Technology Hamirpur on 01/06/2021.

24. Invited Talk on "Emerging Nanoscale devices for Future Technology nodes" in the 6-days AICTE sponsored FDP on "Emerging Trends and Challenges in VLSI Mixed-Signal Processing for Fourth Industrial Revolution" organized by Kongunadu College of Engineering and Technology Trichy on 12/04/2021.

25. Invited Talk on "Next generation solar cell for terrestrial and space applications" in the 6-days QIP sponsored FDP on "Photovoltaic Technology: From Devices to Systems" organized by Indian Institute of Technology Indore on 13/03/2021.

26. Invited Talk on "Emerging Nanoscale Devices for future technology nodes", in the 13-days AICTE sponsored FDP on "Emerging Trends and Challenges in VLSI Mixed Signal Processing for Fourth Industrial Revolution" organized by Kongunadu College of Engineering and Technology, Trichy on 10 March, 2021.

27. Invited Talk on "Emerging Nanoscale Devices for future technology nodes", in the 13-days AICTE sponsored FDP on "Emerging Trends and Challenges in VLSI Mixed Signal Processing for Fourth Industrial Revolution" organized by Kongunadu College of Engineering and Technology, Trichy on 17 Feb, 2021.

28. Invited Talk on Scaling of Nano Devices: Opportunities and Challenges, in the 5-days ATAL sponsored faculty development program on "Smart Sensors and their Applications (SSAP-2021)" organized by SRM IST, Chennai on 06 Jan, 2021.

29. Invited Talk on "Scaling of Nano Devices: Opportunities and Challenges", in the 5-days AICTE funded STTP on "Futuristic Applications and Research Opportunities of Nano Electronics in Bio Science" organized by Sathyabama Institute of Science and Technology, Chennai on 14 Dec, 2020.

30. Invited Talk on "Scaling of Nano Devices: Opportunities and Challenges", in the 5-days AICTE funded STTP on "Futuristic Applications and Research Opportunities of Nano Electronics in Bio Science" organized by Sathyabama Institute of Science and Technology, Chennai on 11 Nov, 2020.

31. Invited Talk on "Progress in Semiconductor Device Technology: A Pathway to Follow Moore???s Law", in the 6-days Faculty Development Program on "Recent Advancements in Semiconductor Technologies-RASET 20" organized by SRM IST, Chennai on 14 Oct, 2020.

32. Invited Talk on "Recent trends in semiconductor devices and future perspectives", in the five day online Faculty Development Program on "Opportunities and Challenges in Next-Generation Semiconductor Devices" organized by Anil Neerukonda Institute of Technology & Sciences, Visakhapatnam, AP on 16 June, 2020.

33. Invited Talk on "Recent Trends in Semiconductor Devices and Future Perspectives" in the one day webinar organized by SNS College of Technology, Coimbatore on 29 July, 2020.

34. Invited Talk on "Progress in Semiconductor Devices for Future Technology Nodes" in the 5-day faculty development program on Next Generation Semiconductor Devices: Modeling and Simulation organized by KL University Andhra Pradesh on 04 August, 2020.

35. Organized a three day SERB sponsored workshop on "BATTERY TECHNOLOGY FOR E-VEHICLE" from 26-28th Dec, 2019.

36. Organized a two day HACKATHON "THEME 1 : SMART INNOVATIVE GLOVE BOX DESIGN and HACKATHON THEME 2 : RECYCLING TECHNIQUES FOR lI-ION BATTERIES", from 28-29th Dec, 2019 with prize money of 1 Lakh.

37. Successfully conducted the five days "Hands-on-Training Program on Technical Writing and Publishing with Advanced Computer Tools" during 25th-29th May, 2019.

38. Successfully conducted the two days workshop on "Technical Writing and Publishing with Advanced Computer Tools: Hands-On Training" during 8th-9th September, 2018.

39. Successfully conducted a two day "Conclave on Materials and Technologies in Energy Conversion and Storage (MTECS 2018)" on e-Vehicle during 28th-29th, December, 2018.

40. PIC Institute Sports

41. Departmental Ph.D. Research Coordinator

42. PIC Tech fest "VASHISHT"

43. Co-PI in Design Innovation Center (DIC), IIITDM Kancheepuram

44. Admin of Institute Social Media

1. Digital System Testing and Testable Design

2. Analog Circuits

3. MOS Modeling for VLSI Circuits

4. VLSI Technology

5. VlSI System Design

6. VLSI Design

7. Digital Systems Engineering

1. S Routray, K P Pradhan, "Theory of Nanostructured Kesterite Solar Cell" in Springer, 2022.

2. K P Pradhan, "An Introduction to Nanoscale CMOS Technology Transistor: A Future Perspective" in Taylor and Francis, 2021.

3. S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, "A new nanoscale DG MOSFET design with enhanced performance a comparative study," in Signal Processing and Information Technology, Ser. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, Springer International Publishing, 2014.

1. V Rajakumari, K P Pradhan, "BTBT based LIF Junctionless FET neuron with plausible mimicking efficiency", IEEE Transactions on Nanotechnology, 2023. (Accepted-In Press)

2. Rameez Raja Shaik, L Chandrasekar, K P Pradhan, "A Robust-Compact Model to Emulate Neuro-Mimetic Dynamics with doped-HfO2 Ferroelectric-FET based Neurons", IEEE Transactions on Nanotechnology, 2023. (Accepted)

3. Rameez Raja Shaik, K P Pradhan, "Investigation on Impact of doped HfO2 thin film ferro-dielectrics on FDSOI NCFET under Back-Gate Bias Influence", IEEE Transactions on Nanotechnology, vol. 22, pp. 14-19, 2022.

4. Shibi Varku, K P Pradhan, S Routray, "Retrieving Carrier population and Collection Efficiency in CFTS/ CFTSe based Solar Cell using Low-dimensional Multiple Nanostructures", Physica Status Solidi A: Applications and Materials Science, vol. 219, no. 22, pp. 2200567, 2022.

5. R R Shaik, K P Pradhan, "Investigation on performance degradation due to induced interface trapped charges on HSO based FDSOI NCFET and sustaining it through back-gate bias", Semiconductor Science and Technology, vol. 37, pp. 105019, 2022.

6. V Rama Seshu, R R Shaik, K P Pradhan, "Impact of unpreventable induced interface trapped charges on HZO based FDSOI NCFET", Microelectronics Reliability, vol. 139, pp. 114748, 2022.

7. V Sakshi, V Rajakumari, K P Pradhan, "Deep Insights of SiGe PNPN Tunnel FET Cavity based Biosensors for Label Free Detection", Silicon, 2022. (Accepted - In Press)

8. Shibi Varku, S Routray, K P Pradhan, "Performance limitation of Cu2FeSnS4 solar cell: Understanding impact of density of defect states", Optical Materials, vol. 133, pp. 112885, 2022.

9. V Rajakumari, K P Pradhan, "Demonstration of an ultra-low energy PD-SOI FinFET based LIF Neuron for SNN", IEEE Transactions on Nanotechnology, vol. 21, pp. 434-441, 2022.

10. L Chandrasekar, K P Pradhan, "Computationally Efficient Region-Wise Potential Based Extremely Closed-Form Analytical Modeling of B/N Substitution Doped GFETs", IEEE Transactions on Electron Devices, vol. 69, no. 8, pp. 4708-4716, 2022.

11. R R Shaik, L Chandrasekar, J-P Raskin, K P Pradhan, "Back-gate bias effect on the linearity of pocket doped FDSOI MOSFET", Microelectronics Journal, Elsevier, vol. 121, pp. 105365, 2022.

12. L Chandrasekar, K P Pradhan, "Memoryless Linearity in Undoped and B-Doped Graphene FETs: A Relative Investigation to Report Improved Reliability", Microelectronics Reliability, Elsevier, vol. 125, pp. 114363, 2021.

13. L Sravani, S Routray, M Courel, K P Pradhan, "Loss Mechanisms in CZTS and CZTSe Kesterite Thin-film Solar Cells: Understanding the Complexity of Defect Density", Solar Energy, Elsevier, vol. 227, pp. 56-66, 2021.

14. L Chandrasekar, K P Pradhan, "Self-Consistent Modeling of B or N Substitution Doped Bottom Gated Graphene FET with Non-Zero Bandgap", IEEE Transactions on Electron Devices, vol. 68, no. 7, pp. 3658 - 3664, 2021.

15. L Sravani, S Routray, K P Pradhan, M Courel, "Kesterite Thin Film Solar Cell: Role of Grain Boundaries and Defects in CZTS and CZTSe", Physica Status Solidi A: Applications and Materials Science, Wiley, May, 2021.

16. A Sariki, K V Rao, L Chandrasekar, R R Shaik, K P Pradhan, "Is Accumulation or Inversion Mode Dielectric Modulated FET Better for Label-Free Biosensing?: A Comparative Investigation", AEU International Journal of Electronics and Communications, vol. 137, no. 153791, pp. 1-7, Elsevier, April, 2021.

17. G S Sahoo, S Routray, K P Pradhan, G P Mishra, "Electrical, Optical and Reliability Analysis of QD Embedded Kesterite Solar Cell", IEEE Transactions on Electron Devices, April, 2021.

18. L Chandrasekar, K. P. Pradhan, "Memoryless Nonlinearity in B-Substitution Doped and Undoped Graphene FETs: A Comparative Investigation" IET Circuits, Devices & Systems, Feb, 2021.

19. B Vandana, S K Mohapatra, J K Das, K P Pradhan, A Kundu, B K Kaushik, "Memoryless Nonlinearity in IT JL FinFET with Spacer Technology: Investigation towards Reliability", Microelectronics Reliability, Elsevier, Feb, 2021.

20. Chinmay Dimri, G. P. Nikhil, P. K. Mohanty, K.P. Pradhan, R. Agarwal, S. Routray, "Investigating Single Event Transients of Advanced Fin Based Devices for Inclusion in ICs", AEÜ - International Journal of Electronics and Communications, Elsevier, Feb, 2021.

21. S Routray, K P Pradhan, G P Mishra, "Effect of Nanostructure on Carrier Transport Mechanism of III-Nitride and Kesterite Solar Cells: A Computational Analysis", IEEE Journal of the Electron Devices Society, 2020.

22. L Sravani, S Routray, K P Pradhan, "Towards Quantum Efficiency Enhancement of Kesterite Nanostructured Absorber: A Prospective of Carrier Quantization Effect", Applied Physics Letters, 2020. (Chosen as Featured Article by the Editors)

23. R Priyanka, Chandrasekar L, R R Shaik, K P Pradhan, "Label Free DNA Detection Techniques using Dielectric Modulated FET: Inversion or Tunneling?", IEEE Sensors Journal, 2020.

24. G. P. Nikhil, Chinmay Dimir, P. K. Mohanty, K.P. Pradhan, G. P. Mishra, S. Routray, "Geomerically-Engineered SMG FinFET Structures at 10nm: RF/DC Performance and Effect of Temperature Analysis", Silicon, Springer, 2020.

25. N Laxmi, S Routray, K P Pradhan, “Effect of Strain-Modulated Multiple Quantum Wells on Carrier Dynamics and Spectral Sensitivity of III-Nitride Photosensitive Devices”, IEEE Sensors Journal, vol. 20, no. 10, pp. 5204-5212, 2020.

26. A Samal, K P Pradhan, S K Mohapatra, "Improvising the switching ratio through low-k / high-k spacer and dielectric gate stack in 3D FinFET - A simulation Perspective", Silicon, Springer, 2020.

27. A Samal, K P Pradhan, S K Mohapatra, "Extensive Study of Underlap Length Effect for 3-D SOI FinFET to Achieve High Switching Ratio and Low Power", Silicon, Springer, 2020.

28. R Raja Shaik, Arun G, L Chandrasekar, K P Pradhan, “A study of workfunction variation in pocket doped FD-SOI technology towards temperature analysis”, Silicon, Springer, 2020.

29. N Laxmi, S Routray, K P Pradhan, “III-Nitride/Si Tandem Solar Cell for High Spectral Response: Key Attributes of Auto-tunneling Mechanisms”, Silicon, Springer, 2019.

30. A Vishnu Priya, V Shiva Prasad, R Raja Shaik, K P Pradhan, “An Optimized Ge Pocket SOI JLT with Efforts to Improve the Self-Heating Effect: Doping & Materials Perspective”, Silicon, Springer, 2019.

31. K P Pradhan, Samar K. Saha, L. Artola, P. K. Sahu, “3-D TCAD assessment of fin based hybrid devices under heavy ion irradiation in 20-nm technology”, IEEE Transactions on Device and Materials Reliability, vol. 18, no. 3, pp. 474-480, 2018.

32. K P Pradhan, Samar K. Saha, P. K. Sahu, Priyanka, “Impact of Fin Height and Fin Angle Variation on the Performance Matrix of Hybrid FinFETs”, IEEE Transactions on Electron Devices, vol. 64, no. 1, pp. 52-57, 2017.

33. S. K. Mohapatra, K P Pradhan, D. Singh, and P. K. Sahu, “The Role of Geometry Parameters and Fin Aspect Ratio of sub-20nm SOI-FinFET: An Analysis towards Analog and RF Circuit Design”, IEEE Transactions on Nanotechnology, vol. 14, no. 3, pp. 546 - 554, 2015.

34. K P Pradhan, P.K. Sahu, “Benefits of Asymmetric Underlap Dual-k Spacer Hybrid FinFET over Bulk FinFET”, IET Circuits, Devices & Systems, Vol. 10, no. 5, pp. 441-447, 2016.

35. K P Pradhan, Priyanka, P. K. Sahu, “Study of fin tapering effect in nanoscale symmetric dual-k spacer (SDS) hybrid FinFETs”, Materials Science in Semiconductor Processing, Vol. 57, pp. 185–189, 2017. (Elsevier)

36. K P Pradhan, M.G.C. Andrade, P. K. Sahu, “Pros and cons of symmetrical dual-k spacer technology in hybrid FinFETs”, Superlattices and Microstructures, vol. 100, pp. 335-341, 2016. (Elsevier)

37. K P Pradhan, Priyanka, Mallikarjunarao, P.K. Sahu, “Exploration of symmetric high-k spacer (SHS) hybrid FinFET for high performance application,” Superlattices and Microstructures, vol. 90, pp. 191-197, 2016. (Elsevier)

38. K P Pradhan, Priyanka, P.K. Sahu, “Temperature dependency of double material gate oxide (DMGO) symmetric dual-k spacer (SDS) wavy FinFET,” Superlattices and Microstructures, vol. 89, pp. 355-361, 2016. (Elsevier)

39. K P Pradhan, Priyanka, P.K. Sahu, “Investigation of asymmetric high-k underlap spacer (AHUS) hybrid FinFET from temperature perspective”, Microsystem Technologies, vol. 23, pp. 2921-2926, 2017. (Springer)

40. K. P. Pradhan, P. K. Sahu, D. Singh, L. Artola, and S. K. Mohapatra, “Reliability analysis of charge plasma based double material gate oxide (DMGO) SiGe-on-insulator (SGOI) MOSFET”, Superlattices and Microstructures, vol. 85, pp. 149-155, 2015. (Elsevier)

41. K P Pradhan, S. K. Mohapatra, and P. K. Sahu, “Impact of Channel and Metal Gate Work Function on GS-DG MOSFET: A Linearity Analysis”, ECS J. Solid State Sci. Technol., vol. 9, no. 9, pp. 393-397, 2015. (ECS)

42. K P Pradhan, S. K. Mohapatra, P. K. Sahu, “Design Equivalent Scaling on Double Gate FinFET towards Analog & RF FOMs: A TCAD Estimation”, Journal of Low Power Electronics, Vol. 11, no. 3, pp. 316-322, 2015. (American Scientific Publisher)

43. S R Panda, K P Pradhan, and P. K. Sahu “Device and Circuit Performance of Si-Based Accumulation-mode CGAA CMOS Inverter” Materials Science in Semiconductor Processing, Elsevier, vol. 66, pp. 87-91, 2017. (Elsevier)

44. K P Pradhan, S. K. Mohapatra, P. K. Sahu, and D. K. Behera, “Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET”, Microelectronics Journal, vol. 45, no. 2, pp. 144-151, 2014. (Elsevier)

45. Rajeev Ranjan, Mallikarjunarao, K P Pradhan and P K Sahu, “A comprehensive investigation of silicon film thickness of nanoscale DG TFET for low power applications”, Adv. Nat. Sci.: Nanosci. Nanotechnol, vol. 7, no. 3, 2016. (IOP Science)

46. Mallikarjunarao, Rajeev Ranjan, K P Pradhan, P.K. Sahu, “Dielectric engineered symmetric underlap double gate tunnel FET (DGTFET): An investigation towards variation of dielectric materials”, Superlattices and Microstructures, vol. 96, pp. 226-233, 2016. (Elsevier)

47. Mallikarjunarao, Rajeev Ranjan, K P Pradhan, L. Artola, P.K. Sahu, “Spacer engineered Trigate SOI TFET: An investigation towards harsh temperature environment applications”, Superlattices and Microstructures, vol. 97, pp. 70-77, 2016. (Elsevier)

48. M K Yadav, K P Pradhan and P K Sahu, “A complete analytical potential based solution for a 4H-SiC MOSFET in nanoscale”, Adv. Nat. Sci.: Nanosci. Nanotechnol., vol. 7, pp. 025011-6, 2016. (IOP Science)

49. P. K. Sahu, S. K. Mohapatra, and K P Pradhan, “Zero temperature-coefficient bias point over wide range of temperatures for single-and double-gate UTB-SOI n-MOSFETs with trapped charges”, Materials Science in Semiconductor Processing, vol. 31, pp. 175-183, 2015. (Elsevier)

50. S. K. Mohapatra, K P Pradhan, L. Artola, and P. K. Sahu, “Estimation of Analog/RF FOMs using Device Design Engineering in GS-DG-MOSFET”, Materials Science in Semiconductor Processing, vol. 31, pp. 455-462, 2015. (Elsevier)

51. S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Temperature dependence inflection point in Ultra-Thin Si directly on Insulator (SDOI) MOSFETs: An influence to key performance metrics”, Superlattices and Microstructures, vol. 78, pp. 134-143, 2015. (Elsevier)

52. K P Pradhan, M. R. Kumar, S. K. Mohapatra, P. K. Sahu, “Analytical modeling of threshold voltage for Cylindrical Gate All Around (CGAA) MOSFET using center potential”, Ain Shams Engineering Journal, vol. 6, pp. 1171-1177, 2015. (Elsevier)

53. B Jena, K P Pradhan, S Dash, G P Mishra, P K Sahu and S K Mohapatra, “Performance analysis of undoped cylindrical gate all around (GAA) MOSFET at subthreshold regime”, Advances in Natural Sciences: Nanoscience and Nanotechnology, vol. 6, pp. 1-4, 2015. (IOP Science)

54. B Jena, K P Pradhan, P K Sahu, S Dash, G P Mishra, S K Mohapatra, “Investigation on Cylindrical Gate All Around (GAA) to Nanowire MOSFET for Circuit Application”, Facta Universitatis, Series: Electronics and Energetics, vol. 28, no. 4, pp. 637-643, 2015. (Facta Universitatis)

55. S. K. Mohapatra, K P Pradhan, G. S. Pati, and P. K. Sahu, “Relative appraisal of Ultra-Thin Body MOSFETs: An analytical modeling including hot carrier induced degradation", Journal of Microelectronics Electronic Components and Materials, vol. 45, pp. 57-65, 2015. (MIDEM Society)

56. S. K. Mohapatra, K P Pradhan, P. K. Sahu, “ZTC bias point of advanced fin based device: The importance and exploration”, Facta Universitatis, Series: Electronics and Energetics, vol. 28, no. 3, pp. 393-405, 2015.

57. K P Pradhan, S K Mohapatra, P K Sahu, S Parija, “Impact of Strain on Fully Depleted Strained Gate Stack Double Gate MOSFET: A Simulation Study”, ECTI Transactions on Electrical Eng., Electronics, and Communications, Vol.13, No.2, pp. 54-57, August 2015.

58. S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Improved Performance in GS-DG-MOSFET with Dual Material Gate and Lateral Asymmetric Channel”, Int. J. of Nano and Biomaterials, Inderscience, vol. 5, no. 4, 2014.

59. P. K. Sahu, S. K. Mohapatra, and K P Pradhan, “Impact of Down-scaling on Analog/RF Performance of sub-100nm GS-DG MOSFET”, Journal of Microelectronics Electronic Components and Materials, vol. 44, no. 2, pp. 119-125, Mar. 2014. (MIDEM Society)

60. S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Resolving the bias point for wide range of temperature applications in high-k/metal gate nanoscale DG-MOSFET”, Facta Universitatis, Series: Electronics and Energetics, vol. 27, no. 4, pp. 613-619, Dec. 2014. (Facta Universitatis)

61. S. K. Mohapatra, K P Pradhan, P. K. Sahu, G. S. Pati, and M. R. Kumar, “The effect of interface trapped charges in DMG-S-SOI MOSFET: a perspective study”, Advances in Natural Sciences: Nanoscience and Nanotechnology, vol. 5, no. 4, pp. 1-7, Nov. 2014. (IOP Science)

62. S. K. Mohapatra, K P Pradhan, P. K. Sahu, and M. R. Kumar, “The performance measure of GS-DG MOSFET: an impact of metal gate work function”, Advances in Natural Sciences: Nanoscience and Nanotechnology, vol. 5, no. 2, pp. 1-6, Mar. 2014. (IOP Science).

63. M. R. Kumar, S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “A Simple Analytical Center Potential Model for Cylindrical Gate All Around (CGAA) MOSFET”, Journal of Electron Devices, vol. 19, pp. 1648-1653, Mar. 2014. (JelDev)

64. P. K. Sahu, S. K. Mohapatra, and K P Pradhan, “A Study of SCEs and Analog FOMs in GS-DG-MOSFET with Lateral Asymmetric Channel Doping”, Journal of Semiconductor Technology and Science, vol. 13, no. 6, pp. 647-654, Dec. 2013. (IEIE, Korea)

65. K P Pradhan, S. K. Mohapatra, P. K. Agarwal, P. K. Sahu, D. K. Behera, and J. Mishra, “Symmetric DG-MOSFET with gate and channel engineering: A 2-D simulation study”, Microelectronics and Solid State Electronics, vol. 2, no. 1, pp. 1-9, Feb. 2013. (Scientific & Academic Publishing, USA)

66. S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Some Device De-sign Considerations to Enhance the Performance of DG-MOSFETs”, Transactions on Electrical And Electronic Materials, vol. 14, no. 6, pp. 291-294, Dec. 2013. (Korean Institute of Electrical and Electronic Material Engineers)

67. S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Nanoscale SOI N-MOSFETS with different gate engineering having biaxial strained channel-a superlative study”, Journal of Electron Devices, vol. 15, pp. 1261-1268, Sep. 2012. (JelDev)

68. S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Investigation of Prefabrication Models of Double Gate MOSFETs in Nanoscale for High Performance Circuit Application”, Nano Trends: A Journal of Nanotechnology and Its Applications, vol. 13, pp. 40-44, Oct. 2012. (Nano Science and Technology Consortium)

1. V Rajakumari, S R Panda, K P Pradhan, "1T FDSOI Based LIF Neuron Without Reset Circuitry: A Proposal and Investigation", 6th IEEE EDTM, South Korea, 2023.

2. Rameez Raja Shaik, L Chandrasekar, V Rajakumari, K P Pradhan, "A Robust-Compact Model to Imitate the Neuronal Dynamics With 2T Based FeFET-MOSFET Capturing Temperature Effects", 6th IEEE ICEE, Bangalore, India, December, 2022.

3. L Chandrasekar, Rameez Raja Shaik, K P Pradhan, "An Analytical Model to Emulate the Biological Synapses Using B or N Substitution Doped Graphene FET With Hysteresis Engineering", 6th IEEE ICEE, Bangalore, India, December, 2022.

4. V Rama Seshu, R R Shaik, K P Pradhan, "RF Linearity/Non-Linearity FoMs analysis of FDSOI NCFET in presence of interface trap charges", 19th IEEE INDICON, Kerala, India, November, 2022.

5. Shibi Varku, S Routray, K P Pradhan, "Contribution of Carrier Quantization Effect towards Performance of Nanostructured CFTS / CFTSe Solar Cells", IEEE Latin American Electron Devices Conference (LAEDC), Mexico, July, 2022.

6. Shibi Varku, S Routray, K P Pradhan, "Understanding the Effect of Interface Trap States on Electrical and Optical Performance of CFTS Thin Film Solar Cell", IEEE Region 10 Symposium (TENSYMP), Bombay, July, 2022.

7. A S Dhruthi, V Rajakumari, K P Pradhan, "An Energy Efficient LIF Neuron Based on Bulk MOSFET with an N+ Buried Layer", IEEE Region 10 Symposium (TENSYMP), Bombay, July, 2022.

8. M Aravind, Shibi Varku, S Routray, K P Pradhan, "Investigation on Electrical and Optical Properties of Cu2FeSnSe 4 (CFTSe) Based Thin Film Solar Cell for Terrestrial Applications", IEEE Region 10 Symposium (TENSYMP), Bombay, July, 2022.

9. Sowparna P, V Rajakumari, K P Pradhan, "A Proposal of Energy Efficient Ferroelectric PDSOI LIF Neuron for Spiking Neural Network Applications", IEEE 16th Nanotechnology Materials and Devices Conference (NMDC), Vancouver, December, 2021.

10. L Chandrasekar, K P Pradhan, "2-Terminal Boron Substitution Doped Metal-Insulator-Graphene (MIG): Modeling and Investigation of Region-Based Electrostatics", IEEE 16th Nanotechnology Materials and Devices Conference (NMDC), Vancouver, December, 2021.

11. R R Shaik, K P Pradhan, "Investigation of Temperature Variation on a HSO Ferroelectric FDSOI NCFET", IEEE 16th Nanotechnology Materials and Devices Conference (NMDC), Vancouver, December, 2021.

12. R R Shaik, K P Pradhan, "Impact of HZO and HSO Thin Film Ferroelectric on FDSOI NCFET", IEEE 21st International Conference on Nanotechnology, Canada, July, 2021.

13. V Rama Seshu, R R Shaik, K P Pradhan, "Effect of Temperature on Performance of HZO Based FD-SOI NCFET", IEEE EuroSOI-ULIS, Caen, France, September, 2021.

14. Monika Shree K, M Jayadeep Reddy, K P Pradhan and Tejendra Dixit, "Development of Multi-physics Modeling of Plasmonics in the UV Region Using Transition Metals", IEEE Latin American Electron Device Conference, 2021.

15. Mooli Shashank Reddy, Tejendra Dixit and K P Pradhan, "Steep Subthreshold Swing in Double Gate NCFET:A Simulation Study", IEEE Latin American Electron Device Conference, 2021.

16. L Chandrasekar, K P Pradhan, "Carrier Density and Quantum Capacitance Model for Doped Graphene", IEEE Electron Devices Technology and Manufacturing, Penang, March, 2020.

17. Nikhil G P, S R Routray, K P Pradhan, "Assessment of Analog/RF Performances for 10 nm Tri-metal Gate FinFET", IEEE Electron Devices Technology and Manufacturing, Penang, March, 2020.

18. S R Routray, K P Pradhan, G P Mishra, "Performance Enhancement of Double Quantum Well Solar Cell by Strain-Modulated Piezo-Phototronics Effect", IEEE Electron Devices Technology and Manufacturing, Penang, March, 2020.

19. Rameez R Shaik, K P Pradhan, "Linearity Behavior of a Pocket Doped p-type Ground Plane FDSOI: Impact of Back Biasing", IEEE International Conference on Emerging Electronics (ICEE), Delhi, Nov, 2020.

20. L Sravani, S Routray, K P Pradhan, "CZTSe Kesterite Solar Cell: The Impact of Defects on Loss Mechanisms", IEEE International Conference on Emerging Electronics (ICEE), Delhi, Nov, 2020.

21. P K Mohanty, G P V Y Nikhil, Chinmay Dimri, K P Pradhan, S Routray, "Estimation of Inverter Characteristics with 10nm FinFET Architectures", IEEE International Conference on Emerging Electronics (ICEE), Delhi, Nov, 2020.

22. L Chandrasekar, K P Pradhan, "Modeling the Electrostatics of 2-Terminal Boron or Nitrogen Substitution Doped Metal-Insulator-Graphene (MIG) Structure", IEEE International Conference on Emerging Electronics (ICEE), Delhi, Nov, 2020.

23. Shashank Reddy Mooli, T Dixit, K P Pradhan, "DOUBLE GATE NCFET: A New Approach To Achieve Low subthreshold Swing", IEEE International Conference on Emerging Electronics (ICEE), Delhi, Nov, 2020.

24. Bhargav N C, T Dixit, A N Pranavi, K P Pradhan, "Modelling of Temperature Variation Effect on the Memristance", IEEE International Conference on Emerging Electronics (ICEE), Delhi, Nov, 2020.

25. A N Pranavi, T Dixit, K P Pradhan, "Towards the Development of Unified Models for Memristors: Charge–Flux Relationship", IEEE International Conference on Emerging Electronics (ICEE), Delhi, Nov, 2020.

26. Nikhil G P, S R Routray, K P Pradhan, "Assessment of Analog/RF Performances for 10 nm Tri-metal Gate FinFET", IEEE Electron Devices Technology and Manufacturing, Penang, March, 2020.

27. L Chandrasekar, K P Pradhan, "Carrier Density and Quantum Capacitance Model for Doped Graphene", IEEE Electron Devices Technology and Manufacturing, Penang, March, 2020.

28. S R Routray, K P Pradhan, G P Mishra, "Performance Enhancement of Double Quantum Well Solar Cell by Strain-Modulated Piezo-Phototronics Effect", IEEE Electron Devices Technology and Manufacturing, Penang, March, 2020.

29. Chandrasekar L, K P Pradhan, Pintu Kumar, "Comparative Study on Nonlinearity of Doped and Undoped GFET using DC Characteristics", 16th IEEE INDICON, Rajkot, December, 2019.

30. L Chandrasekar, K P Pradhan, "Linearity Study of Doped Graphene FET using DC Characteristics", Symposium on 2D Materials and Devices, Jodhpur, September, 2019.

31. A Vishnu Priya, V Shiva Prasad, K P Pradhan, "Optimization of Ge-pocket JLFET: An approach to extend the scalable limit", IEEE ICESIP, Chennai, July, 2019.

32. N Laxmi, S R Routray, K P Pradhan, "InGaN/Si Hetero-Junction Tandem Solar Cell with Self Tunneling Effect: Proposal & Analysis", IEEE EuroSOI-ULIS, Grenoble, France, April, 2019.

33. Arun G, S R Routray, K P Pradhan, "Effect of AlGaN layer in GaN/InGaN/GaN Superlattice Solar Cell", ICONN, Chennai, Jan., 2019.

34. Rameez Raja Shaik, Arun G, K P Pradhan, “Electrically Modified SOI Structure to Reduce the Leakage”, IEEE India Council International Conference (INDICON), Coimbatore, Dec., 2018.

35. Arun G, S R Routray, K P Pradhan, “Effect of Polarization Induced 2DEG on Carrier Dynamics of GaN/In_{x}Ga_{1-x}N Based Planar Solar Cells”, IEEE International Conference on Emerging Electronics (ICEE), Bengaluru, Dec., 2018.

36. K P Pradhan, P K Sahu, “RF and Noise performance exploration of Double Gate FinFET”, International Conference on Advances in Computing, Control and Networking, Bangkok, Thailand, Feb., 2017.

37. K P Pradhan, P K Sahu, Mallikarjunarao, “Heavy-Ion Irradiation effect in Trigate SOI Tunnel FETs with high-k Spacer Technology”, IEEE TENCON 2016, Singapore, Nov., 2016.

38. K P Pradhan, P K Sahu, Rajeev Ranjan, “Investigation on Asymmetric Dual-k Spacer (ADS) Trigate Wavy FinFET: A Novel Device”, 3rd International Conference on Devices, Circuits and Systems (ICDCS), Coimbatore, March, 2016.

39. B Vandana, P Parashar, J K Das, K P Pradhan, S Patro, S K Mohapatra, “Mole fraction dependency electrical performances of extremely thin SiGe on insulator junctionless channel transistor (SGOI JLCT)”, International Conference on Signal Processing and Communication, Noida, March, 2018.

40. Mallikarjuna Rao, Rajeev Ranjan, K P Pradhan, P K Sahu, “Performance Analysis of Symmetric High-k Spacer (SHS) Trigate SOI TFET”, 3rd International Conference on Devices, Circuits and Systems (ICDCS), Coimbatore, March, 2016.

41. K P Pradhan, Priyanka, P K Sahu, “Exploration of Double Material Gate Oxide in Symmetric Dual-k Spacer Wavy FinFET”, International Conference on Emerging Technologies: Micro to Nano (ETMN), Jaipur, October, 2015.

42. K P Pradhan, Mallikarjunarao, Priyanka, P K Sahu, “Analysis of Symmetric High-k Spacer (SHS) Trigate Wavy FinFET: A Novel Device”, IEEE Indicon, Delhi, Dec., 2015.

43. K P Pradhan, D. Singh, S. K. Mohapatra, P. K Sahu, “Double Material Gate Oxide (DMGO) SiGe-on-Insulator (SGOI) MOSFET: A proposal and analysis”, IEEE Electron Devices and Solid-State Circuits (EDSSC), Singapore, June, 2015.

44. K P Pradhan, D Singh, S K Mohapatra, P K Sahu, “Assessment of III-V FinFETs at 20 nm node: A Process variation analysis”, International Conference on Recent Trends in Computing (ICRTC), Delhi, March, 2015.

45. D Singh, K P Pradhan, S K Mohapatra, P K Sahu, “Optimization of Underlap Length for DGMOSFET and FinFET”, International Conference on Recent Trends in Computing (ICRTC), Delhi, March, 2015.

46. D. Singh, S. Panda, S. K. Mohapatra, K. P. Pradhan, P. K. Sahu, “Performance Analysis of UTB-DG MOSFET over SG MOSFET”, International Conference on Micro-electronics and Communication and Computation, San Diego, USA, Feb. 2015.

47. S. K. Mohapatra, K P Pradhan, P. K. Sahu, D. Singh, and S. Panda, “Ultra-Thin Si Directly on Insulator (SDOI) MOSFETs at 20 nm gate length”, IEEE International Conference on High Performance Computing and Applications, Bhubaneswar, Odisha, India, Dec. 2014.

48. D. Singh, S. Panda, S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Static performance analysis on UTB-SG and DG MOSFETs with Si and III-V channel materials”, IEEE International Conference on High Performance Computing and Applications, Bhubaneswar, Odisha, India, Dec. 2014.

49. D. Singh, S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Variation study of process parameters in Trigate SOI-FinFET”, IEEE INDICON, Emerging Trends and Innovation in Technology, Pune, India, Dec. 2014.

50. S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Linearity and Analog Performance Analysis in GSDG-MOSFET with Gate and Channel Engineering”, IEEE INDICON, Emerging Trends and Innovation in Technology, Pune, India, Dec. 2014.

51. S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Improved Performance in GS-DG-MOSFET with Dual Material Gate and Lateral Asymmetric Channel," International Conference on Automatic Control, Modelling & Simulation, Brasov, Romania, Jun. 2014.

52. K P Pradhan, P. K. Agarwal, P. K. Sahu, and S. K. Mohapatra, “Role of high-k materials in Nanoscale TM-DG MOSFET: A simulation study”, National Conference on Recent Developments in Electronics, New Delhi, India, Jan. 2013.

53. S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “A new nanoscale DG MOSFET design with enhanced performance a comparative study”, Signal Processing and Information Technology, Springer Publishing, Dubai, Dec., 2012.

54. P. K. Agarwal, K P Pradhan, S. K. Mohapatra, and P. K. Sahu, “Insulating layer parameters are still in reduction of kink”, IEEE Nirma University International Conference on Engineering, Ahmedabad, Dec. 2012.

55. K P Pradhan, P. K. Agarwal, S. K. Mohapatra, and P. K. Sahu, “The impact of high-k gate dielectric materials over short channel parameters on sub-100 nm MOSFET”, National Seminar on Ferroelectrics & Dielectrics, Bhubaneswar, India, Dec. 2012.

56. S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Effect of channel & gate engineering on Double Gate (DG) MOSFET-A comparative study”, IEEE International Conference on Emerging Electronics, Bombay, India, Dec. 2012.

57. K P Pradhan, S. K. Mohapatra, and P. K. Sahu, “An analytical surface potential and threshold voltage model of fully depleted strained-SOI MOSFETs in nanoscale with high-k gate oxide”, IEEE International Conference on Emerging Technology Trends in Electronics, Communication and Networking, Surat, Gujarat, India, Dec., 2012.

58. S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Investigation of dimension effects of FD-S-SOI MOSFET in nanoscale”, IEEE International Conference on Emerging Technology Trends in Electronics, Communication and Networking, Surat, Gujarat, India, Dec., 2012.