Faculty

Dr. Kumar Prasannajit Pradhan

Assistant Professor

E-mail: kppradhan@iiitdm.ac.in | Ph: 044-2747-6373 | Room No: 108A, Academic Building

Google Scholar: https://scholar.google.co.in/citations?user=VeRNC6YAAAAJ&hl=en

Researchgate: https://www.researchgate.net/profile/K_P_Pradhan

Linkedin: https://www.linkedin.com/in/dr-k-p-pradhan-0173544b/

Education

National Institute of Technology Rourkela

Rourkela

Nanoelectronic Devices

2013 - 2017

National Institute of Technology Rourkela

Rourkela

Nanoelectronic Devices

2011 - 2013

Specialization

  1. Electronics & Communication Engineering

  2. Nanoelectronics

  3. VLSI Technology

Research Interests

  1. Modeling & Simulation of Nanoscale Devices, SOI MOSFETs, FinFETs, Negative Capacitance FETs, Radiation Hardened Devices

Honours + Awards + Recognitions

  1. Snigdhashri Patra Memorial Gold Medal for Best Ph.D. Thesis of 2016-17 by National Institute of Technology Rourkela

  2. Availed International Travel Grant from SERB, DST under Young Scientist Award, 2016

  3. Best paper award in the virtual presentation in ICMCC, San Diego, 2015

  4. Reviewer of IEEE Transactions on Electron Devices

  5. Reviewer of IET Circuits, Devices & Systems

  6. Member of Editorial Board of Frontiers of Mechatronics

  7. Member of TPC in International Conference on Signal Processing and Communication (ICSC-2018)

  8. Reviewer of Microelectronics Journal, Superlattices & Microstructures, Material Science in Semiconductor Processing, Physica-E: Low Dimensional Systems & Nanostructures, Elsevier

  9. Reviewer of Nanotechnology, IOP Science

  10. Reviewer of International Journal of Electronics, Taylor & Francis

  11. Reviewer of Analog Integrated Circuit & Signal Processing, Pramana Journal of Physics, Springer

Work Experience

Teaching

  1. Assistant Professor in Electronics & Communication Engineering in Jaypee Institute of Information Technology Noida from July 2017 to March 2018

Research

  1. Senior Project Engineer at Nanolab, Indian Institute of Technology Kanpur from March-July, 2017

Professional Membership

  1. Member, Institute of Electrical and Electronics Engineers (IEEE)

Professional Service

  1. Co-PI in Design Innovation Center (DIC), IIITDM Kancheepuram

  2. Member of Institute website maintenance team

  3. Admin of Institute Social Media

Teaching

  1. Electrical Science-I

  2. Electrical Science-II

  3. Digital Communication

  4. Analog Electronics

  5. Analog Electronics Lab

Books

  1. S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, "A new nanoscale DG MOSFET design with enhanced performance a comparative study," in Signal Processing and Information Technology, Ser. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, Springer International Publishing, 2014.

Journal Publications

  1. K P Pradhan, Samar K. Saha, P. K. Sahu, Priyanka, “Impact of Fin Height and Fin Angle Variation on the Performance Matrix of Hybrid FinFETs”, IEEE Transactions on Electron Devices, vol. 64, no. 1, pp.-52-57, 2017.

  2. K P Pradhan, P.K. Sahu, “Benefits of Asymmetric Underlap Dual-k Spacer Hybrid FinFET over Bulk FinFET”, IET Circuits, Devices & Systems, Vol. 10, no. 5, pp. 441-447, 2016.

  3. K P Pradhan, Priyanka, P. K. Sahu, “Study of fin tapering effect in nanoscale symmetric dual-k spacer (SDS) hybrid FinFETs”, Materials Science in Semiconductor Processing, Vol. 57, pp. 185–189, 2017. (Elsevier)

  4. K P Pradhan, M.G.C. Andrade, P. K. Sahu, “Pros and cons of symmetrical dual-k spacer technology in hybrid FinFETs”, Superlattices and Microstructures, vol. 100, pp. 335-341, 2016. (Elsevier)

  5. K P Pradhan, Priyanka, Mallikarjunarao, P.K. Sahu, “Exploration of symmetric high-k spacer (SHS) hybrid FinFET for high performance application,” Superlattices and Microstructures, vol. 90, pp. 191-197, 2016. (Elsevier)

  6. K P Pradhan, Priyanka, P.K. Sahu, “Temperature dependency of double material gate oxide (DMGO) symmetric dual-k spacer (SDS) wavy FinFET,” Superlattices and Microstructures, vol. 89, pp. 355-361, 2016. (Elsevier)

  7. K P Pradhan, Priyanka, P.K. Sahu, “Investigation of asymmetric high-k underlap spacer (AHUS) hybrid FinFET from temperature perspective”, Microsystem Technologies, vol. 23, pp. 2921-2926, 2017. (Springer)

  8. S. K. Mohapatra, K P Pradhan, D. Singh, and P. K. Sahu, “The Role of Geometry Parameters and Fin Aspect Ratio of sub-20nm SOI-FinFET: An Analysis towards Analog and RF Circuit Design”, IEEE Transactions on Nanotechnology, vol. 14, no. 3, pp. 546 - 554, 2015.

  9. K. P. Pradhan, P. K. Sahu, D. Singh, L. Artola, and S. K. Mohapatra, “Reliability analysis of charge plasma based double material gate oxide (DMGO) SiGe-on-insulator (SGOI) MOSFET”, Superlattices and Microstructures, vol. 85, pp. 149-155, 2015. (Elsevier)

  10. K P Pradhan, S. K. Mohapatra, and P. K. Sahu, “Impact of Channel and Metal Gate Work Function on GS-DG MOSFET: A Linearity Analysis”, ECS J. Solid State Sci. Technol., vol. 9, no. 9, pp. 393-397, 2015. (ECS)

  11. K P Pradhan, S. K. Mohapatra, P. K. Sahu, “Design Equivalent Scaling on Double Gate FinFET towards Analog & RF FOMs: A TCAD Estimation”, Journal of Low Power Electronics, Vol. 11, no. 3, pp. 316-322, 2015. (American Scientific Publisher)

  12. S R Panda, K P Pradhan, and P. K. Sahu “Device and Circuit Performance of Si-Based Accumulation-mode CGAA CMOS Inverter” Materials Science in Semiconductor Processing, Elsevier, vol. 66, pp. 87-91, 2017. (Elsevier)

  13. K P Pradhan, S. K. Mohapatra, P. K. Sahu, and D. K. Behera, “Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET”, Microelectronics Journal, vol. 45, no. 2, pp. 144-151, 2014. (Elsevier)

  14. Rajeev Ranjan, Mallikarjunarao, K P Pradhan and P K Sahu, “A comprehensive investigation of silicon film thickness of nanoscale DG TFET for low power applications”, Adv. Nat. Sci.: Nanosci. Nanotechnol, vol. 7, no. 3, 2016. (IOP Science)

  15. Mallikarjunarao, Rajeev Ranjan, K P Pradhan, P.K. Sahu, “Dielectric engineered symmetric underlap double gate tunnel FET (DGTFET): An investigation towards variation of dielectric materials”, Superlattices and Microstructures, vol. 96, pp. 226-233, 2016. (Elsevier)

  16. Mallikarjunarao, Rajeev Ranjan, K P Pradhan, L. Artola, P.K. Sahu, “Spacer engineered Trigate SOI TFET: An investigation towards harsh temperature environment applications”, Superlattices and Microstructures, vol. 97, pp. 70-77, 2016. (Elsevier)

  17. M K Yadav, K P Pradhan and P K Sahu, “A complete analytical potential based solution for a 4H-SiC MOSFET in nanoscale”, Adv. Nat. Sci.: Nanosci. Nanotechnol., vol. 7, pp. 025011-6, 2016. (IOP Science)

  18. P. K. Sahu, S. K. Mohapatra, and K P Pradhan, “Zero temperature-coefficient bias point over wide range of temperatures for single-and double-gate UTB-SOI n-MOSFETs with trapped charges”, Materials Science in Semiconductor Processing, vol. 31, pp. 175-183, 2015. (Elsevier)

  19. S. K. Mohapatra, K P Pradhan, L. Artola, and P. K. Sahu, “Estimation of Analog/RF FOMs using Device Design Engineering in GS-DG-MOSFET”, Materials Science in Semiconductor Processing, vol. 31, pp. 455-462, 2015. (Elsevier)

  20. S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Temperature dependence inflection point in Ultra-Thin Si directly on Insulator (SDOI) MOSFETs: An influence to key performance metrics”, Superlattices and Microstructures, vol. 78, pp. 134-143, 2015. (Elsevier)

  21. K P Pradhan, M. R. Kumar, S. K. Mohapatra, P. K. Sahu, “Analytical modeling of threshold voltage for Cylindrical Gate All Around (CGAA) MOSFET using center potential”, Ain Shams Engineering Journal, vol. 6, pp. 1171-1177, 2015. (Elsevier)

  22. B Jena, K P Pradhan, S Dash, G P Mishra, P K Sahu and S K Mohapatra, “Performance analysis of undoped cylindrical gate all around (GAA) MOSFET at subthreshold regime”, Advances in Natural Sciences: Nanoscience and Nanotechnology, vol. 6, pp. 1-4, 2015. (IOP Science)

  23. B Jena, K P Pradhan, P K Sahu, S Dash, G P Mishra, S K Mohapatra, “Investigation on Cylindrical Gate All Around (GAA) to Nanowire MOSFET for Circuit Application”, Facta Universitatis, Series: Electronics and Energetics, vol. 28, no. 4, pp. 637-643, 2015. (Facta Universitatis)

  24. S. K. Mohapatra, K P Pradhan, G. S. Pati, and P. K. Sahu, “Relative appraisal of Ultra-Thin Body MOSFETs: An analytical modeling including hot carrier induced degradation", Journal of Microelectronics Electronic Components and Materials, vol. 45, pp. 57-65, 2015. (MIDEM Society)

  25. S. K. Mohapatra, K P Pradhan, P. K. Sahu, “ZTC bias point of advanced fin based device: The importance and exploration”, Facta Universitatis, Series: Electronics and Energetics, vol. 28, no. 3, pp. 393-405, 2015.

  26. K P Pradhan, S K Mohapatra, P K Sahu, S Parija, “Impact of Strain on Fully Depleted Strained Gate Stack Double Gate MOSFET: A Simulation Study”, ECTI Transactions on Electrical Eng., Electronics, and Communications, Vol.13, No.2, pp. 54-57, August 2015.

  27. S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Improved Performance in GS-DG-MOSFET with Dual Material Gate and Lateral Asymmetric Channel”, Int. J. of Nano and Biomaterials, Inderscience, vol. 5, no. 4, 2014.

  28. P. K. Sahu, S. K. Mohapatra, and K P Pradhan, “Impact of Down-scaling on Analog/RF Performance of sub-100nm GS-DG MOSFET”, Journal of Microelectronics Electronic Components and Materials, vol. 44, no. 2, pp. 119-125, Mar. 2014. (MIDEM Society)

  29. S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Resolving the bias point for wide range of temperature applications in high-k/metal gate nanoscale DG-MOSFET”, Facta Universitatis, Series: Electronics and Energetics, vol. 27, no. 4, pp. 613-619, Dec. 2014. (Facta Universitatis)

  30. S. K. Mohapatra, K P Pradhan, P. K. Sahu, G. S. Pati, and M. R. Kumar, “The effect of interface trapped charges in DMG-S-SOI MOSFET: a perspective study”, Advances in Natural Sciences: Nanoscience and Nanotechnology, vol. 5, no. 4, pp. 1-7, Nov. 2014. (IOP Science)

  31. S. K. Mohapatra, K P Pradhan, P. K. Sahu, and M. R. Kumar, “The performance measure of GS-DG MOSFET: an impact of metal gate work function”, Advances in Natural Sciences: Nanoscience and Nanotechnology, vol. 5, no. 2, pp. 1-6, Mar. 2014. (IOP Science).

  32. M. R. Kumar, S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “A Simple Analytical Center Potential Model for Cylindrical Gate All Around (CGAA) MOSFET”, Journal of Electron Devices, vol. 19, pp. 1648-1653, Mar. 2014. (JelDev)

  33. P. K. Sahu, S. K. Mohapatra, and K P Pradhan, “A Study of SCEs and Analog FOMs in GS-DG-MOSFET with Lateral Asymmetric Channel Doping”, Journal of Semiconductor Technology and Science, vol. 13, no. 6, pp. 647-654, Dec. 2013. (IEIE, Korea)

  34. K P Pradhan, S. K. Mohapatra, P. K. Agarwal, P. K. Sahu, D. K. Behera, and J. Mishra, “Symmetric DG-MOSFET with gate and channel engineering: A 2-D simulation study”, Microelectronics and Solid State Electronics, vol. 2, no. 1, pp. 1-9, Feb. 2013. (Scientific & Academic Publishing, USA)

  35. S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Some Device De-sign Considerations to Enhance the Performance of DG-MOSFETs”, Transactions on Electrical And Electronic Materials, vol. 14, no. 6, pp. 291-294, Dec. 2013. (Korean Institute of Electrical and Electronic Material Engineers)

  36. S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Nanoscale SOI N-MOSFETS with different gate engineering having biaxial strained channel-a superlative study”, Journal of Electron Devices, vol. 15, pp. 1261-1268, Sep. 2012. (JelDev)

  37. S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Investigation of Prefabrication Models of Double Gate MOSFETs in Nanoscale for High Performance Circuit Application”, Nano Trends: A Journal of Nanotechnology and Its Applications, vol. 13, pp. 40-44, Oct. 2012. (Nano Science and Technology Consortium)

Conference Publications

  1. K P Pradhan, P K Sahu, “RF and Noise performance exploration of Double Gate FinFET”, International Conference on Advances in Computing, Control and Networking, Bangkok, Thailand, Feb., 2017.

  2. K P Pradhan, P K Sahu, Mallikarjunarao, “Heavy-Ion Irradiation effect in Trigate SOI Tunnel FETs with high-k Spacer Technology”, IEEE TENCON 2016, Singapore, Nov., 2016.

  3. K P Pradhan, P K Sahu, Rajeev Ranjan, “Investigation on Asymmetric Dual-k Spacer (ADS) Trigate Wavy FinFET: A Novel Device”, 3rd International Conference on Devices, Circuits and Systems (ICDCS), Coimbatore, March, 2016.

  4. B Vandana, P Parashar, J K Das, K P Pradhan, S Patro, S K Mohapatra, “Mole fraction dependency electrical performances of extremely thin SiGe on insulator junctionless channel transistor (SGOI JLCT)”, International Conference on Signal Processing and Communication, Noida, March, 2018.

  5. Mallikarjuna Rao, Rajeev Ranjan, K P Pradhan, P K Sahu, “Performance Analysis of Symmetric High-k Spacer (SHS) Trigate SOI TFET”, 3rd International Conference on Devices, Circuits and Systems (ICDCS), Coimbatore, March, 2016.

  6. K P Pradhan, Priyanka, P K Sahu, “Exploration of Double Material Gate Oxide in Symmetric Dual-k Spacer Wavy FinFET”, International Conference on Emerging Technologies: Micro to Nano (ETMN), Jaipur, October, 2015.

  7. K P Pradhan, Mallikarjunarao, Priyanka, P K Sahu, “Analysis of Symmetric High-k Spacer (SHS) Trigate Wavy FinFET: A Novel Device”, IEEE Indicon, Delhi, Dec., 2015.

  8. K P Pradhan, D. Singh, S. K. Mohapatra, P. K Sahu, “Double Material Gate Oxide (DMGO) SiGe-on-Insulator (SGOI) MOSFET: A proposal and analysis”, IEEE Electron Devices and Solid-State Circuits (EDSSC), Singapore, June, 2015.

  9. K P Pradhan, D Singh, S K Mohapatra, P K Sahu, “Assessment of III-V FinFETs at 20 nm node: A Process variation analysis”, International Conference on Recent Trends in Computing (ICRTC), Delhi, March, 2015.

  10. D Singh, K P Pradhan, S K Mohapatra, P K Sahu, “Optimization of Underlap Length for DGMOSFET and FinFET”, International Conference on Recent Trends in Computing (ICRTC), Delhi, March, 2015.

  11. D. Singh, S. Panda, S. K. Mohapatra, K. P. Pradhan, P. K. Sahu, “Performance Analysis of UTB-DG MOSFET over SG MOSFET”, International Conference on Micro-electronics and Communication and Computation, San Diego, USA, Feb. 2015.

  12. S. K. Mohapatra, K P Pradhan, P. K. Sahu, D. Singh, and S. Panda, “Ultra-Thin Si Directly on Insulator (SDOI) MOSFETs at 20 nm gate length”, IEEE International Conference on High Performance Computing and Applications, Bhubaneswar, Odisha, India, Dec. 2014.

  13. D. Singh, S. Panda, S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Static performance analysis on UTB-SG and DG MOSFETs with Si and III-V channel materials”, IEEE International Conference on High Performance Computing and Applications, Bhubaneswar, Odisha, India, Dec. 2014.

  14. D. Singh, S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Variation study of process parameters in Trigate SOI-FinFET”, IEEE INDICON, Emerging Trends and Innovation in Technology, Pune, India, Dec. 2014.

  15. S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Linearity and Analog Performance Analysis in GSDG-MOSFET with Gate and Channel Engineering”, IEEE INDICON, Emerging Trends and Innovation in Technology, Pune, India, Dec. 2014.

  16. S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Improved Performance in GS-DG-MOSFET with Dual Material Gate and Lateral Asymmetric Channel," International Conference on Automatic Control, Modelling & Simulation, Brasov, Romania, Jun. 2014.

  17. K P Pradhan, P. K. Agarwal, P. K. Sahu, and S. K. Mohapatra, “Role of high-k materials in Nanoscale TM-DG MOSFET: A simulation study”, National Conference on Recent Developments in Electronics, New Delhi, India, Jan. 2013.

  18. S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “A new nanoscale DG MOSFET design with enhanced performance a comparative study”, Signal Processing and Information Technology, Springer Publishing, Dubai, Dec., 2012.

  19. P. K. Agarwal, K P Pradhan, S. K. Mohapatra, and P. K. Sahu, “Insulating layer parameters are still in reduction of kink”, IEEE Nirma University International Conference on Engineering, Ahmedabad, Dec. 2012.

  20. K P Pradhan, P. K. Agarwal, S. K. Mohapatra, and P. K. Sahu, “The impact of high-k gate dielectric materials over short channel parameters on sub-100 nm MOSFET”, National Seminar on Ferroelectrics & Dielectrics, Bhubaneswar, India, Dec. 2012.

  21. S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Effect of channel & gate engineering on Double Gate (DG) MOSFET-A comparative study”, IEEE International Conference on Emerging Electronics, Bombay, India, Dec. 2012.

  22. K P Pradhan, S. K. Mohapatra, and P. K. Sahu, “An analytical surface potential and threshold voltage model of fully depleted strained-SOI MOSFETs in nanoscale with high-k gate oxide”, IEEE International Conference on Emerging Technology Trends in Electronics, Communication and Networking, Surat, Gujarat, India, Dec., 2012.

  23. S. K. Mohapatra, K P Pradhan, and P. K. Sahu, “Investigation of dimension effects of FD-S-SOI MOSFET in nanoscale”, IEEE International Conference on Emerging Technology Trends in Electronics, Communication and Networking, Surat, Gujarat, India, Dec., 2012.

Institute Login
© IIITDM Kancheepuram 2017
Best viewed in Safari, Chrome and Firefox.