Research Scholar

Dinesh Ganesan

Ph.D - Electronics and Communication Systems 2014

E-mail: edm14d003@iiitdm.ac.in

Area of Research

Circuit Simulator Development & Mixed Signal Circuit Design

Education

College of Engineering - Guindy

Chennai

ME- VLSI Design

2010 - 2012

Work Experience

Bharat Electronics Limited

Chennai

Deputy Engineer - Development and Engineering

2012 - 2013

Vellore Institute of Technology

Vellore

Assistant Professor

Aug 2012 - Nov 2012

Publications

QSCsim - Charge Based Switched Capacitor Simulator

Dec 2016

B. J. Kailath and G. Dinesh, "QSCsim -Charge Based Switched Capacitor Simulator," 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Gwalior, 2016

Improved alias rejection using interleaved CIC decimation filter

June 2016

S. Karthikeyan, Dinesh G. and B. J. Kailath, "Improved alias rejection using interleaved CIC decimation filter,"2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), Vancouver, BC, 2016

Switched Capacitor Circuit Simulator in Q-V Domain including Non Idealities

May 2016

Muralidhar Gadamsetty, G.Dinesh and Binsu J Kailath, "Switched Capacitor Circuit Simulator in Q-V Domain including Non Idealities“, 20th VLSI Design and Test Symposium (VDAT-2016), IIT Guwahati, May 24-27, 2016.

Institute Login
© IIITDM Kancheepuram 2017
Best viewed in Safari, Chrome and Firefox.