High Performance Reconfigurable Computing System Engineering Group
A One Week Workshop on High Performance Computing for ALL
Date: 02 to 06 December 2019
Venue @IIITDM Kancheepuram, Melakottaiyur, Vandalur-Kelambakkam Road, Chennai - 600 127
Objective This workshop aims to provide the basics of modern processor architecture and serial optimization techniques that can effectively exploit the architectural features for scientific computing. Critical issues in data movement and issues in high performance computing are discussed. The use of parallel processing in shared, nonuniform access, and distributed memories is discussed. In addition the popular programming styles of OpenMP, MPI and mixed programming are highlighted. Hands on sessions will be conducted on the IIITDM Cluster Computer.
Organized By Center for High Performance Reconfigurable Computing, Department of Computer Science and Engineering, Indian Institute of Information Technology Design and Manufacturing (IIITDM) Kancheepuram. IIITDM Kancheepuram is an Institute of National Importance under Ministry of Human Resources Development, Govt. of India. IIITDM Kancheepuram is established in the year 2007 with a vision to excel as a center for excellence in IT enabled Design and Manufacturing. This workshop is aligned to the vision statement of the Institute to develop the human resources in programming of super computer or high performance computer.
Topics to be Covered
  • Introduction to HPC
  • Modern Processor Architecture
  • Optimization of Serial Code
  • Profiling of Program and functions
  • Parallel Computer
  • Parallelization Fundamentals
  • Shared memory models and programming languages and OpenMP
  • Distributed Memory Architectures and MPI Programming
  • Vector Processors, GPUs and CUDA Programming
Target Audience Faculty/Scientists/Researchers/M. Tech/MCA/BCA and B. Tech Students working in the area of computation engineering.
Prerequisite Participant should have the working knowledge of basic computer programming in C.
Background of Previous Events CHRC has very good expertise in organizing the workshop in a well planned manner. The details of the previous workshops, budget and feedback from the participant can be found at Click Here
Registration Details
  • Online Registration - Open from Aug 15, 2019.
  • Payment Link: (USE: HPCWS2019) Click Here
  • Registration Link: Click HERE
  • Registration Closes by December 01, 2019.
Registration Fees
R&D Labs/ Faculty/ PSUs
Research Scholars, M. Tech & B. Tech Students
Rs. 1,000* NON REFUNDABLE
* Inclusive of 18% GST as per GoI norms and 15% Institute Overheads.
Important Details
  • NEFT or IMPS Account Details: IIITDM Educational Events; Acc.No:35594334673; State Bank of India; Kandigai Branch; IFSC code: SBIN0018365.
  • Registration Fee covers only refreshments charges during the workshop for all the 5 days.
  • Registration Fee Does NOT cover Lunch and Accommodation charges.
  • No TA/DA will be provided.
  • Please mail payment receipt to noor@iiitdm.ac.in, in order to Get Confirmation
  • Maximum Number of Seats 30
Accommodation
  • For Accommodation please contact Hostel office, IIITDM Kancheepuram, Email: hosteloffice@iiitdm.ac.in
  • Hostel Room Fee: Rs.150 per Day per Head
  • Guest House: AC - Rs.750/-; Non-AC - 450.
  • For Accommodation Please call Hostel office: Mr Pakkir Swamy - 88255 47293
Contact Info: Dr Noor Mahammad S
Workshop Organizing Chair
Indian Institute of Information Technology,
Design and Manufacturing (IIITDM) Kancheepuram
Melakottaiyur, Vandalur - Kelambakkam Road,
Chennai - 600 127, Tamil Nadu, India.

For enquiry and clarification, please contact:
Email: noorse@gmail.com; 044-2747 6349/ 91760 10587(M)
How to Reach Venue (www.iiitdm.ac.in): IIITDM Kancheepuram Campus in Chennai on Vandalur - Kelambakkam Road.
It is 9KMs from Vandalur Zoo toward East Direction, Landmark: KANDIGAI.
Schedule

DAY 1

10 DEC 19, MON

09.00-09.30AM

Registration

09.45-10.15AM

ZoWP followed by Tea Break

10.15-11.00AM

Introduction to HPC

11.00-12.30PM

Modern Processor Architecture, ILP and TLP

12.30-02.00PM

Lunch Break

02.00-03.30PM

Parallel Computer Architecture

03.30-04.00PM

Tea Break

04.00-05.30PM

Memory Access and Profiling

DAY 2

11 DEC 19, TUE

09.00-10.30AM

Introduction to OpenMP

10.30-11.00AM

Tea Break

11.00-12.30PM

Practice Session1 on OpenMP: Parallel Programming using OpenMP

12.30-02.00PM

Lunch Break

02.00-03.30PM

Practice Session2 on OpenMP: OpenMP Deadloack and Data races

03.30-04.00PM

Tea Break

04.00-05.30PM

Practice Session3 on OpenMP: Parallel Programming with OpenMP Sections

DAY 3

12 DEC 19, WED

09.00-10.30AM

Introduction to MPI

10.30-11.00AM

Tea Break

11.00-12.30PM

Practice Session1 on MPI: Parallel Programming using Collective Communication

12.30-02.00PM

Lunch Break

02.00-03.30PM

Practice Session2 on MPI: Parallel Programming using Collective Communication

03.30-04.00PM

Tea Break

04.00-05.30PM

Practice Session3 on MPI: MPI work sharing and Loading

DAY 4

13 DEC 19, THU

09.00-10.30AM

Point to Point Communication using MPI

10.30-11.00AM

Tea Break

11.00-12.30PM

Practice Session4 on MPI: Point to Point Communication using MPI

12.30-02.00PM

Lunch Break

02.00-03.30PM

Practice Session5 on MPI: Point to Point Communication using MPI

03.30-04.00PM

Tea Break

04.00-05.30PM

Practice Session6 on MPI: Point to Point Communication using MPI

DAY 5

14 DEC 19,  FRI

09.00-10.30AM

GPGPU Architecture

10.30-11.00AM

Tea Break

11.00-12.30PM

Introduction to CUDA Programming

12.30-02.00PM

Lunch Break

02.00-03.30PM

Practice Session on CUDA

03.30-04.00PM

Tea Break

04.00-05.30PM

Presentation on Project Work

Thank You!!