High Performance Reconfigurable Computing System Engineering Group
A One Week Workshop on
Reconfigurable Computing: FPGA based System Design
Date: 09 to 13 December 2019
Venue @IIITDM Kancheepuram, Melakottaiyur, Vandalur-Kelambakkam Road, Chennai - 600 127
Objective This workshop aims to provide the basics of reconfigurable computing, importance of reconfigurable computing, architectures of CPLD and FPGAs, Design implementation on FPGA prototype board. Programmable ASIC Design methodology. CPLD and FPGA Architectures and programming. Evolvable Hardware and Fault Tolerant Reconfigurable Computing. Image/Video Processing on FPGA prototype board.
Organized By Center for High Performance Reconfigurable Computing, Department of Computer Science and Engineering, Indian Institute of Information Technology Design and Manufacturing (IIITDM) Kancheepuram. IIITDM Kancheepuram is an Institute of National Importance under Ministry of Human Resources Development, Govt. of India. IIITDM Kancheepuram is established in the year 2007 with a vision to excel as a center for excellence in IT enabled Design and Manufacturing. This workshop is aligned to the vision statement of the Institute to develop the human resources in System on Programmable Chip, Reconfigurable Computing and Fast Prototyping on FPGAs.
Topics to be Covered
  • Introduction to Reconfigurable Computing and paradigms of computing.
  • Reconfigurable Configurable Hardware- Device Architecture, Reconfigurable Computing Architecture, Reconfigurable Computing Systems, Reconfigurable Management.
  • Programming Reconfigurable Systems - Compute Models and System Architectures, Programming FPGA Applications in HDLs
  • Programmable ASICs Design Methodology
  • CPLD and FPGA Architectures and Programming
  • Evolvable Hardware
  • Fault Tolerant Reconfigurable Computing
  • Image/Video Processing System implementation on FPGA
Target Audience Faculty/Scientists/Researchers/M. Tech/MCA and B. Tech Students working in the area of FPGAs and Reconfigurable Computing.
Prerequisite Participant should have the working knowledge of basic understanding of Digital Logic Design, VLSI Design and HDL Programming.
Background of Previous Events CHRC has very good expertise in organizing the workshop in a well planned manner. The details of the previous workshops, budget and feedback from the participant can be found at Click Here
Registration Details
  • Online Registration - Open from Aug 15, 2019.
  • Payment Link: (USE: RCWS2019) Click Here
  • Registration Link: Click HERE
  • Registration Closes by December 01, 2019.
Registration Fees
R&D Labs/ Faculty/ PSUs
Research Scholars, M. Tech & B. Tech Students
Rs. 1,000* NON REFUNDABLE
* Inclusive of 18% GST as per GoI norms and 15% Institute Overheads.
Important Details
  • NEFT or IMPS Account Details: IIITDM Educational Events; Acc.No:35594334673; State Bank of India; Kandigai Branch; IFSC code: SBIN0018365.
  • Registration Fee covers refreshments charges during the workshop for all the 5 days.
  • Registration Fee Does NOT cover Lunch and Accommodation charges.
  • No TA/DA will be provided.
  • Please mail payment receipt to noor@iiitdm.ac.in, in order to Get Confirmation
  • Maximum Number of Seats 30
Accommodation
  • For Accommodation please contact Hostel office, IIITDM Kancheepuram, Email: hosteloffice@iiitdm.ac.in
  • Hostel Room Fee: Rs.150 per Day per Head
  • Guest House: AC - Rs.750/-; Non-AC - 450.
  • For Accommodation Please call Hostel office: Mr Pakkir Swamy - 88255 47293
Contact Info: Dr Noor Mahammad S
Workshop Organizing Chair
Indian Institute of Information Technology,
Design and Manufacturing (IIITDM) Kancheepuram
Melakottaiyur, Vandalur - Kelambakkam Road,
Chennai - 600 127, Tamil Nadu, India.

For enquiry and clarification, please contact:
Email: noorse@gmail.com; 044-2747 6349/ 91760 10587(M)
How to Reach Venue (www.iiitdm.ac.in): IIITDM Kancheepuram Campus in Chennai on Vandalur - Kelambakkam Road.
It is 9KMs from Vandalur Zoo toward East Direction, Landmark: KANDIGAI.
Schedule:

DAY 1

10 DEC 19, MON

09.00-09.30AM

Registration

09.45-10.15AM

ZoWP followed by Tea Break

10.15-11.00AM

Introduction to Reconfigurable Computing

11.00-12.30PM

Programmable ASIC Design Methodology

12.30-02.00PM

Lunch Break

02.00-03.30PM

Practice Session1:  Introduction to HDL and Tools

03.30-04.00PM

Tea Break

04.00-05.30PM

Practice Session2:  FPGA Design Flow

DAY 2

11 DEC 19, TUE

09.00-10.30AM

CPLD and FPGA Architectures

10.30-11.00AM

Tea Break

11.00-12.30PM

Reconfigurable Computing Mechanisms and Management

12.30-02.00PM

Lunch Break

02.00-03.30PM

Practice Session3: Block RAM initialization and Experiments

03.30-04.00PM

Tea Break

04.00-05.30PM

Practice Session4: IO Interfacing for FPGA Board

DAY 3

12 DEC 19, WED

09.00-10.30AM

Reconfigurable Computing Models

10.30-11.00AM

Tea Break

11.00-12.30PM

Packet Processing using FPGAs

12.30-02.00PM

Lunch Break

02.00-03.30PM

Practice Session5: Image/Video Processing Building blocks Design

03.30-04.00PM

Tea Break

04.00-05.30PM

Practice Session6: Image/Video Processing Building blocks Design

DAY 4

13 DEC 19, THU

09.00-10.30AM

Evolvable Hardware

10.30-11.00AM

Tea Break

11.00-12.30PM

Evolvable Hardware

12.30-02.00PM

Lunch Break

02.00-03.30PM

Practice Session7: Image Processing System Design

03.30-04.00PM

Tea Break

04.00-05.30PM

Practice Session8: Image Processing System Design

DAY 5

14 DEC 19,  FRI

09.00-10.30AM

Fault Tolerant Reconfigurable Computing

10.30-11.00AM

Tea Break

11.00-12.30PM

Fault Tolerant Reconfigurable Computing

12.30-02.00PM

Lunch Break

02.00-03.30PM

Practice Session9: Video Processing System Design

03.30-04.00PM

Tea Break

04.00-05.30PM

Practice Session10: Video Processing System Design

Thank You!!