A. K. Jain and A. Singha, "Sub-10 nm scalability of emerging nanowire junctionless FETs using a Schottky metallic Core," Springer Journal of Electronic Materials, January 2021.
A. K. Jain, and M. Jagadesh Kumar, “Sub-10 nm scalability of SOI-JLFETs using a ground plane in a high-K BOX: A Simulation Study,” IEEE Access, Vol. 8, pp. 137540-137548, July 2020.
A. K. Jain, Jaspreet Singh, and M. Jagadesh Kumar, “Investigation of the scalability of the emerging Nanotube Junctionless FETs using an intrinsic pocket,” IEEE Journal of the Electron Devices Soc., Vol. 7, pp 888-896, Aug. 2019.
J. Singh, A.K. Jain, and M. Jagadesh Kumar, “Realizing a Planar 4H-SiC Junctionless FET for Sub-10-nm Regime Using P+ Pocket,” IEEE Transactions on Electron Devices, vol. 66, no. 7. pp. 3209- 3204, July 2019.
A. K. Jain, S. Sahay, and Mamidala Jagadesh Kumar, “Controlling L-BTBT in Emerging Nanotube FETs using Dual-material gate,” IEEE Journal of the Electron Devices Soc., vol. 6, pp. 611- 621, Apr. 2018.
A.K. Jain, S. Yadav, M. Mehra, S. Sapra, & M. Singh, “Solution-Processed Cubic GaN for Potential Lighting Applications,” MRS Advances, Vol. 4, Issue 9, pp. 1-8, Feb. 2019.