Professor

Prof. Binsu J Kailath

Email: bkailath@iiitdm.ac.in | Ph: +91-44-27476341

Room: 108 E

Prof. Binsu J Kailath

Education

  • IIT Madras PhD in Ultra Thin Oxide MOS Devices, Dept. of Electrical Engineering

    Chennai 2003 - 2007

  • IIT Madras M.Tech. in MicroElectronics and VLSI Design, Dept. of Electrical Engineering

    Chennai 1999 - 2001

  • University of Calicut B.Tech. in Electronics and Communication Engineering

    Kerala 1988 - 1992

Research Interests

  • Spiking Neural Networks
  • Non-volatile Memory-based In-Memory Computing
  • Application of Neuromorphic Circuits in healthcare domain
  • Mixed Signal IC Design
  • Microelectronics and MEMS
  • M Tech VLSI candidates interested in pursuing PhD in the above domains may please apply to our call for Visvesvaraya PhD scheme in MeitY C2S Project: http://admissions.iiitdm.ac.in/phd_2404/index.php

Work Experience

  • Teaching

    • Faculty Member in Electronics Engineering in College of Engineering, Chengannur, Kerala, for 8 years
    • Faculty Member in Electronics Engineering in IIITDM Kancheepuram from Oct 2008
  • Industry

    • Neuromorphic Circuit Design (Analog and Digital Circuit Design - Ongoing)
    • Switch Capacitor circuit simulator Development (Completed-GUI remaining)
    • Sigma Delta ADC (ongoing, fabrication is planned in SCL, Punjab under SMDP-C2SD sponsored
    • by MeitY))
    • Composite PFD based PLL (design is completed and fabrication is planned in SCL, Punjab under SMDP-C2SD sponsored by MeitY)
    • Fabrication, characterization and extraction of conduction Mechanisms in SiC MIS Capacitors with High-k dielectrics of which fabrication and characterization was carried out in Centre for Nano Science and Engg, IISc Bangalore through INUP (completed)
    • In the sponsored project ???Novel Oxidation Techniques for improvement in the Electrical properties of Ultra-thin SiO2 for VLSI technology??? coordinated by Prof. Nandita DasGupta in Microelectronics and MEMS Laboratory, Dept. of Electrical Engineering, IIT Madras (completed)
    • Study of Novel gate oxidation techniques for future MOS devices (completed)
    • Study of high-k gate dielectrics for future MOS devices (completed)
    • Study of Laser Induced Oxidation as a viable technique to grow ultra thin SiO2 (completed)
    • Study of Rapid thermal Oxidation technique to grow ultra thin SiO2 (completed)
    • Optimization of HNO3 Vapour oxidation technique to grow ultra thin SiO2 (completed)
    • Study of the effect of phosphorus doping on passivation of grain boundaries in poly Si TFTs (completed)